IBIS Model Builder

1 · Component & model

Component name Manufacturer Model name Model type Vinl (V) Vinh (V)

Package & pin parasitics, temperature

R_pkg (Ω) L_pkg (H) C_pkg (F) R_pin (Ω) L_pin (H) C_pin (F) Temp typ (°C) Temp min (°C) Temp max (°C)

Pins — one number name per line (all share the model above)

2 · Where does the data come from?

Process node NMOS width W (µm) NMOS length L (µm) PMOS width W (µm) PMOS length L (µm) C_comp override (pF, blank = estimate)

Standard pad-ring cap for this process ≈ – pF (bond pad + ESD; included in the auto C_comp).

Edit process parameters (square-law)

Vdd (V) Vth,n (V) Vth,p (V) k'n (µA/V²) k'p (µA/V²) λn (1/V) λp (1/V) Cox (fF/µm²)

Supply / swing Vcc (V) Load cap C_load (pF) Rise time (ns) Fall time (ns) Edge definition Pin C_comp (pF)

Vcc (V) Pin C_comp (pF) Rise time (ns) Fall time (ns)

Pulldown I‑V — one Vout,current[A] per line Pullup I‑V — one Vtable(=Vcc-Vout),current[A] per line

Paste a SPICE netlist of your output buffer (supports M... devices and SkyWater X...nfet/pfet... subckt devices with W=/L=)

⚠ A browser can't read a Cadence OA database or a filesystem path directly. This generates a Virtuoso SKILL/OCEAN script that reads your schematic and prints the pin's driver W/L. Run it in the CIW, then paste the numbers (or the netlist) back here.

Read the schematic currently open in Virtuoso (no lib/cell/view needed — uses geGetEditCellView())

Schematic OA path (optional — path to the library dir, e.g. /proj/pdk/my_lib; registers the lib so lib/cell/view resolves)

Library Cell View

PAD net name / pattern (* = wildcard)

Run the above in the Virtuoso CIW. It lists every instance on the PAD net with its W/L — your drivers are the pfet (pull-up) and nfet (pull-down) rows. If nothing prints, the net name didn't match your pattern — the script then lists the cell's actual net names so you can fix the pattern. Most reliable path: it also writes a SPICE netlist you can paste into the Paste SPICE netlist tab. Or paste the whole output into the box below to auto-sum parallel fingers and fill W/L.

Paste the SKILL output here — it sums the widths of parallel fingers (same type, same gate net, same L) and fills W/L below

Process node Pulldown NMOS W (µm) Pulldown NMOS L (µm) Pullup PMOS W (µm) Pullup PMOS L (µm) C_comp override (pF, blank = estimate)

Standard pad-ring cap ≈ – pF (included in auto C_comp).

Live model preview ● updates as you type

Enter inputs above to see the live model diagram.

Transient step response ● 1τ crosshair, up & down

External load C_load (pF)

Enter inputs above to see the step response.

3 · Output

Pulldown (NMOS) Pullup (PMOS) POWER clamp GND clamp C_comp Package R/L/C Ramp