Modern SoCs are split into chiplets that must be re-connected inside the package. The choice of interconnect — plain organic substrate, a silicon interposer, an embedded bridge — sets the achievable die-to-die pitch, bandwidth density, and cost. Select an example:
| Package | Die-to-die medium | Interconnect pitch | Needs silicon? | Rel. cost | Die-to-die BW density | Real-world example |
|---|---|---|---|---|---|---|
| MCM (organic) | package-substrate traces | coarse — C4 ≈130 µm + substrate lines | no | $ | low | AMD server MCMs, RF/PA modules |
| 2.5D interposer | Si-interposer RDL + µbumps | fine — µbump ≈40–55 µm, RDL sub-µm | yes (large interposer + TSVs) | $$$ | very high | GPU + HBM (TSMC CoWoS), Xilinx SSIT |
| EMIB (bridge) | small Si bridge embedded in substrate | fine, but only locally at the die edge | yes (tiny bridge, no big TSVs) | $$ | high (local) | Intel Sapphire Rapids, Stratix FPGAs |
| LGA (board attach) | — not a die-to-die method — | land ≈1 mm (socket) | no | $$ (socket) | n/a | Intel LGA1700, AMD SP5 CPU sockets |
Note: LGA is a board-attach style (the alternative to soldered BGA balls) — it's about how the whole package meets the motherboard, not how two dies talk. It's here because it's the other "substrate" question people ask about.