ESD / IO Pin Tracer
generate SKILL → run in CIW → load the CSV → inspect the pad-to-transistor table
1 · Configure & copy the SKILL to paste in CIW (icfb)
Pin-name regex (which top pins to trace)
Common conventions
PAD / IO prefix (default)
contains "pad" (any case)
PAD_0, PAD_1 …
…PAD / …_PAD_3
ALL-CAPS names
common IO words
CSV output path (on the Cadence host)
📋 Copy SKILL
Paste into the Virtuoso
CIW
with the target schematic open & active. It writes the CSV, which you load in step 2.
2 · Load results
Trace CSV (from the SKILL dump)
no trace loaded —
load bundled sample
Flavor CSV (Cin estimate — from tsmc-transistor-flavors)
no flavor table — Cin will be unavailable
Node (for Cin lookup)
— pick —
Cin source
Database, estimate if unmatched
Database only
Estimate only (ignore database)
Estimate Cox (fF/µm²)
≈ 34.5 / tox(nm) · used per the mode at left
3 · Pad → transistor table
Clear filters
Load a trace CSV (or the sample) to populate the table.