ESD Debug · Master Reference —
SV* / multiphase-buck VR controller · rev A
Captured from working session · sequential

ESD root-cause debug,
end to end.

Everything from the SV* failure-path read through to the bench grounding rules, in the order we worked it. Two damage channels — over-voltage and over-current — carry the whole story.

    Contents

  1. The SV* ESD problem
  2. First principles — two damage channels
  3. Stress models & the pulse-width axis
  4. The clamp — AC trigger + snapback
  5. CDM vs HBM — diagnosis by duration
  6. Terminology
  7. The diagnostic flow
  8. Test configurations — pin grounding
  9. Zapping vs curve tracing
  10. SV* test plan & fixes
  11. References
Chapter 1 · where we started

1. The SV* ESD problem

The pin map shows the SVID signals split across two ESD domains, and the high-voltage outputs sit behind programmable isolation that can strand the discharge.

  • Two-domain SVID. Low-voltage I/O — SVC, SVDL, SVTI, SVTOL — lives in the Pvdd2AnaVddio / prgCustomIo3 group, clamped to PGND. The high-voltage outputs — SVDH, SVTOH — sit in the far-right prgSvidio2VddioHDrive block referenced to VDDIO.
  • The yellow failure path. A positive strike on SVDH must travel up into the VDDIO net, across to the prgVddioCDG clamp, then down to PGND.
  • The stranded path. Two programmable elements poison that route for ESD: the prgVddioSwitch 1 kΩ legs (≈2 kV drop at HBM peak when the bridge FET is off) and the prgGpioR floatwell switch (debiases under a fast transient). If current can't reach the clamp, it crowds into the HDrive PMOS drain junction.
Core suspicion

SVDH/SVTOH are exposed in both channels: a fast edge overshoots the far clamp onto the HDrive gate oxide (voltage), and a long event can't reach the clamp through the 1 kΩ/floatwell so it melts the drain (current). The rest of this document is the framework to prove which.

Chapter 2 · first principles

2. The two damage channels

Strip away the acronyms and silicon dies in exactly two ways. Which one wins depends on what is exceeded first — a critical field or a melting temperature.

The two root-cause channels
ChannelGoverning lawWhat failsSignatureFavoured by
Over-voltage
field-driven		E = V/d > E_crit
(≈6–10 MV/cm SiO₂)		Gate-oxide rupture, junction reverse breakdown, ILD punctureGate leakage; low-ohm G–D/G–S shortFast edges — CDM, IEC first peak
Over-current
thermal-driven		P = I²R → T > T_melt
(Si 1414 °C, Al 660 °C)		2nd breakdown / filamentation, metal & contact fuse, resistor burnoutDrain–source short; junction leakage; opensLong / high-energy — HBM, MM, IEC tail
Cross-section of a lateral n-channel MOSFET showing the thin gate oxide layer between the gate and the silicon channel
(Image couldn't load — see the labeled cross-section at Wikimedia Commons.)
Figure 2.1. Where the field channel strikes. The gate oxide is the thin (≈5–200 nm) SiO₂ dielectric between gate and channel; when E = V/d exceeds ≈6–10 MV/cm it ruptures into a conductive filament — the dominant CDM failure. Cross-section via Wikimedia Commons (see page for license).
Chapter 3 · the axis that matters

3. Stress models & the pulse-width axis

The model names (HBM, CDM…) are just points on a single axis: pulse width. Pulse width decides whether heat or field reaches its limit first.

Peak current share
peak I
HBM3.0%
MM7.4%
CDM22.4%
IEC67.2%
Edge speed, duration & delivered current at each model's qualification level
ModelRiseDurationPeak currentTends to fail
HBM
7.5 ns
150 ns
1.33 A
 I
MM
5 ns
80 ns
3.3 A
 I
CDM
0.3 ns
1.5 ns
10 A
 V
IEC
0.85 ns
60 ns
30 A
 V/I

Bars normalized per column; CDM peak current is order-of-magnitude (package dependent). The orthogonality is the message: CDM = fast & brief (field), HBM = slow & long (thermal), IEC = fast edge and long tail (both).[6][7]

3.1 The Wunsch–Bell crossover

Thermal power-to-failure climbs steeply as pulses shorten (∝1/√τ in the diffusion regime), while the dielectric limit barely moves with time. The device fails at whichever limit is lower — so there is a crossover.[1]

pulse width τ (log) → longer power-to-failure (log) thermal limit (Wunsch–Bell) oxide / field limit (≈const) VOLTAGE wins CURRENT wins CDM HBM EOS
Figure 3.1. Short pulses (CDM) sit where the thermal curve is above the oxide line → over-voltage; long pulses (HBM/EOS) sit where it drops below → over-current. After Wunsch–Bell / Dwyer.[1]

So "longer duration" damages by current. More ∫I²R dt into the same spot → junction melt, metal/contact fuse, resistor burnout — all thermal.

Chapter 4 · the protection device

4. The clamp — AC trigger + snapback

The cells repeated across the pin map (IS_AVNWELL, PVDD2POC, prgVddioCDG…) are all the same: an RC-triggered active MOSFET rail clamp.[5] It turns on two ways.

The clamp's two turn-on mechanisms
MechanismTriggerBehaviourRisk
AC trigger primaryDisplacement current in the RC net — responds to dV/dt, not a fixed voltageTurns the big FET on in ~ns; holds for the RC time-out (hundreds of ns), clamping in triode at low VIf RC/gate drive is slower than the edge (CDM) → overshoot before conduction
Snapback backstopDrain-junction avalanche fires the parasitic NPN (current-triggered)Higher Vt1, then low holding voltage; carries large currentNon-uniform → filamentation if un-ballasted; Vt1 can exceed oxide BV in scaled nodes

4.1 Two phases = two channels

A clamp event has a turn-on/overshoot phase and a conduction phase, and each owns one damage channel.

time → node voltage gate-oxide breakdown turn-on delay CDM (fast) overshoot > BV → oxide ruptures HBM (slow, ~150 ns) conduction plateau V = Vhold + I·Ron + L·di/dt · I < It2
Figure 4.1. Same clamp, two stresses. CDM overshoots oxide BV during the turn-on delay (a voltage kill in the first ns); HBM is clamped low but parks the cell in conduction where the question is current vs It2 (an over-current kill).
Chapter 5 · sanity-checked against literature

5. CDM vs HBM — diagnosis by duration

Three physical claims from the session, each checked against published sources. All three hold.

Physics claims — verdicts
ClaimVerdictWhy (sourced)
HBM (longer) → more current/thermal damage; energy ∫I²R dt accumulates, melts metal/junctionCorrectWunsch–Bell: in the diffusion regime power-to-fail falls as 1/√τ, so longer pulses melt at lower current; HBM (130–170 ns) fails by junction melt & metal fuse.[1][3]
CDM (short, <1 ns) → voltage stress; edge outruns the RC clampCorrectCDM rise <200 ps; documented oxide damage from the ~20 ps initial step before the clamp conducts; oxide rupture is the dominant CDM failure mode.[8][9]
The first-order clamp sees higher voltage during CDMCorrectAn HBM-tuned clamp "may not even turn on before a CDM strike"; residual V = Vhold + I·Ron + L·di/dt, and L·di/dt + capacitive coupling overshoot onto internal gates.[6][10]
Chapter 6 · speak the same language

6. Terminology

Locked-in terms
TermSpelled outWhat it isExample
TLPTransmission Line PulseLab generator making a rectangular ESD-like pulse, defined rise/width; standard ≈100 ns100 ns-TLP @ 3 V
vf-TLPVery Fast TLPUltra-short TLP, ≤10 ns width, <1 ns rise; emulates CDM / IEC first peak1 ns-TLP, 5 ns-TLP
Zap(bench slang)One pulse event applied to the DUT — not a formal term but universal"zapped it at 2 kV HBM"
Curve traceDC I–V measurementForce voltage, measure steady current (SMU / curve tracer). DC, not pulsed. Finds leakage, shorts, openssweep 0→3.3 V, read leakage
Snapback2nd breakdown regionOn a pulsed I–V, current jumps as voltage drops (parasitic NPN on). Invisible to DC curve traceVt1=5.8 V → Vhold=2.1 V
It2 / Vt22nd-breakdown current/voltageThe TLP point where the device fails (thermal limit)It2 = 8 A @ 100 ns
Vt1 / VholdTrigger / holding voltageWhere snapback starts, and the low plateau it holdsVt1=5.8, Vhold=2.1
RdynDynamic resistanceSlope of the snapback region, (Vt2−Vt1)/(It2−It1); lower = better clamp≈0.35 Ω
Chapter 7 · bench workflow

7. The diagnostic flow

Each step measures something that tells you what to measure next.

Pre-stress curve trace (baseline)

DC leakage on the suspect pin and its neighbours, recorded in the same grounding you'll zap in (Ch 8–9). This is your "before" signature.

▼

Read the failure signature

Gate leakage / low-ohm gate short → voltage. Drain–source short / junction leakage → current. Open on a bus → metal fuse.

▼

TLP (100 ns) — measure It2

If current is suspected: sweep to failure, capture Vt1, Vhold, It2, Rdyn. That's the thermal limit in conduction.

▼

vf-TLP (1–5 ns) — measure overshoot

If voltage is suspected: does the node overshoot oxide BV before the clamp turns on? Did snapback trigger?

▼

Pulse-width sweep (1 / 10 / 30 / 100 / 300 ns)

The decisive test. If It2 falls steeply with width → thermal/current. If failure stays oxide regardless of width → field/voltage. Builds your own Wunsch–Bell curve.

▼

CDM vs HBM on an identical pair (validate)

One part CDM, one part HBM. Different signatures → duration is the variable. Same signature → the path/clamp is the limit.

▼

Failure analysis + fix

EMMI / OBIRCH / FIB to pinpoint the filament, then fix the owning phase (faster clamp for voltage, lower-R path / bigger FET for current) and re-qualify.

7.1 How OBIRCH builds its map

OBIRCH (Optical Beam Induced Resistance Change) localizes resistive defects one pixel at a time. A constant voltage holds the net biased; an IR laser (≈1.3 µm, so it works through the silicon backside) is raster-scanned, and at each beam position the laser locally warms the metal. Metal resistance rises with temperature, so under fixed V the supply current shifts by ΔI/I = −ΔR/R. The tool samples that supply current at every pixel and converts it to a resistance-change image.[15] So yes — the map is the supply current measured under constant voltage.

hν (IR laser) ΔR ⇒ ΔI  (V constant) interconnect under test defect (void / high-R) V constant V I measure I (TIA) ΔI sampled per pixel as the laser rasters → smooth normal background outlier at the defect
Figure 7.1. Constant V across the net; the IR laser scans and heats each spot; the supply current I is sampled per pixel. Normal metal gives a smooth background; a resistive defect gives an outsized ΔI spike. Baseline current is rejected continuously by laser modulation + lock-in.[14] Original schematic.
Your model, corrected

Right: constant V, measure supply current, defect = outlier. Refine: it's one raster scan with the no-laser baseline rejected continuously by laser-modulation + lock-in — not two full laser-off / laser-on images subtracted (that's golden-device differencing, a separate method). And the contrast is an anomalous resistance change — high local R, current crowding, or a void that impedes heat spread — not "trapped heat" alone.[15][16]

Concretely, picture the classic V — ammeter — R loop. The chip net is the resistor; constant V holds it biased; the ammeter is the detector. The laser sets where on the die you are (the pixel's x,y); the ammeter reading at that instant is the pixel's value. Raster the beam and the readings fill the 2D map.

constant-V measurement V1 const V R(T) chip net = DUT hν A AM1 · reads I value = I where (x,y) 2D OBIRCH map outlier (x,y) pixel = I at that beam position scan the laser → fill every pixel
Figure 7.2. Each pixel of the map gets its position from where the laser sits and its value from the ammeter current at that instant (constant V). Raster the beam over the whole die and the readings build the image; the spot whose resistance reacts abnormally to the heat lands as an outlier pixel — the defect. (Circuit after the standard V–ammeter–R loop.)
Chapter 8 · how the part is wired during test

8. Test configurations — pin grounding

During a zap, only the pin under test is driven; the rest are either tied to ground or left floating. The default per ANSI/ESD STM5.5.1 and the JS-001 user guide is all other pins grounded — the worst case.[11][12]

A · Pad-to-ground (all others grounded) worst case · standard · most common TLP / zap DUT SVDH (under test) SVDL SVTI SVTOL VDDIO PGND all other pins + supply → GND B · Others floating situational · closer to live operation TLP / zap DUT SVDH (under test) float float float PGND only the return (PGND) grounded · rest floating
Figure 8.1. The two grounding choices. A maximizes coupling between the stressed pad and every other node — the conservative default the standards specify. B leaves non-return pins floating, closer to a live board but less reproducible. Run A for qualification; add B only to chase application-specific coupling.
Grounding configuration options, ranked by how commonly they're used
RankConfigurationPin under testOther I/OSupplyWhen used
1 · most commonPad-to-ground→ sourcegroundedgroundedDefault qualification (HBM/CDM/IEC/TLP); worst-case coupling
2 · commonVdd-to-Vss (rail)Vdd → sourcefloating—Power-rail clamp sizing; isolates the clamp
3 · situationalPad-to-supply→ sourcefloating / groundedfloatingPad referenced to a Vdd domain
4 · nichePin-pair / differentialA + B → sourcegrounded / floatgrounded/floatCoupled diff pairs (LVDS/CML); cross-coupling failures
grounded floating either / conditional
Chapter 9 · keep them consistent

9. Zapping vs curve tracing — same grounding?

The standards mandate grounding for the zap; DC curve tracing has no mandated scheme. Best practice is to match them so the before/after leakage comparison is apples-to-apples — coupling and parasitics are configuration-dependent.[13]

Configuration aspect → TLP / ESD zapping vs DC I–V curve tracing
AspectTLP / ESD zappingDC I–V curve tracing
Pin under test→ TLP source (rectangular pulse, 0→V)→ SMU high (DC sweep 0→V_op)
Other I/O pinsGrounded (Config 1, worst case)Grounded — match the zap
Supply (VDDIO)GroundedGrounded (match)
Ground / PGNDReference (0 V)SMU low / reference (same node)
DrivePulse: ns–µs, high current (A)DC steady-state, low current (pA–µA)
SensingV & I probes on scope (transient)Kelvin / 4-wire (removes lead R)
YieldsVt1, Vhold, It2, Rdyn (snapback I–V)Leakage, shorts/opens, parametric shift
StandardANSI/ESD STM5.5.1; JS-001 (HBM)JESD25 / JESD89 — no mandated scheme; match ESD for correlation
Role in flowStress to failure; get the failure levelBaseline before & signature after
Rule of thumb

Curve-trace with the identical grounding you zap in. Then a jump like 50 pA → 100 µA on the same pin is unambiguous damage, not a coupling artifact.

Chapter 10 · put it to work

10. SV* test plan & fixes

What to run on SVDH / SVTOH, and what each result means
ResultChannelRoot causeFix
Fails vf-TLP (5 ns) but survives 100 ns-TLPVTurn-on overshoot onto HDrive gate oxideFaster trigger (smaller RC, cap multiplier), lower Vt1, dual CDM diodes + secondary clamp at the pad
Fails 100 ns-TLP & HBM; survives vf-TLPIIt2 too low / path strangledTake the 1 kΩ (prgVddioSwitch) & floatwell out of the ESD path; widen bus/vias; enlarge MBIG; ballast
Fails both at similar currentV/IStranded clamp — no good route existsDiff vs a clean pin; if reference passes → extract route R/L; add pad-local dual diode that bypasses the isolation
One-line plan

Curve-trace baseline (Ch 9 grounding) → vf-TLP + 100 ns-TLP both polarities, SVDH→PGND and →VDDIO → pulse-width sweep if ambiguous → diff against a clean VDDIO pin → EMMI/OBIRCH the filament → fix the owning phase.

Chapter 11 · sources

11. References

  1. Wunsch & Bell, "Threshold Failure Levels of Semiconductor Diodes and Transistors Due to Pulse Voltages," IEEE Trans. Nucl. Sci. NS-15, 1968 — power-to-failure vs pulse width. Wunsch–Bell curve figure
  2. "ESD protection design for I/O libraries in advanced CMOS," Solid-State Electronics — fundamental mechanisms; 6–10 MV/cm; 30× melt-resistance drop. sciencedirect S0038110108001664
  3. "HMM–TLP correlation for system-efficient ESD design," Microelectronics Reliability — 100 ns TLP ↔ thermal; oxide is a separate non-thermal channel. sciencedirect S0026271411005117
  4. "Identifying EOS and ESD Failures in Semiconductor Devices," Electronic Design — oxide rupture & filament imagery. electronicdesign.com 21799782
  5. "A MOSFET power-supply clamp with feedback-enhanced triggering," Microelectronics Reliability — RC-triggered active clamp operation. sciencedirect S0026271404001520
  6. onsemi — HBM vs IEC 61000-4-2: 8 kV HBM part can fail at 2 kV IEC; clamp may not turn on before a <1 ns edge. onsemi.com
  7. TI AAJ "Protecting your IC from system-level ESD" (SLYT492) — HBM/CDM/IEC waveform & peak-current comparison. ti.com/lit/an/slyt492
  8. "CDM ESD failure modes and VFTLP testing," EOS/ESD — gate-oxide damage is the dominant CDM failure. esda.org
  9. "Device Failure from the Initial Current Step of a CDM Discharge," In Compliance / EOS-ESD — ~6 V extra drop damages oxide at ~20 ps. incompliancemag.com
  10. "Challenges of CDM Modeling for High-Speed Interface Devices," In Compliance — reflections & voltage overshoots degrade CDM robustness. incompliancemag.com
  11. ANSI/ESD STM5.5.1 (TLP) & SP5.5.2 (vf-TLP), Component Level — non-tested pins to a common ground unless otherwise specified. esda.org standards
  12. ANSI/ESDA/JEDEC JS-001 (HBM) & JTR001 user guide — other pins shorted together and to ground (worst case). jedec.org
  13. Curve tracing & failure analysis best practice — match curve-trace grounding to the ESD test for correlation (Semitracks / RTI). semitracks.com
  14. K. Nikawa, "Optical Beam Induced Resistance Change (OBIRCH): overview and recent results," IEEE / EOS-ESD — 1.3 µm IR works through Si backside; laser-modulation + lock-in for high resolution. globalsino.com/EM/page2852
  15. "Dynamic resistance variation mapping technique for defect isolation," Microelectronics Reliability — conventional OBIRCH uses constant-voltage bias and current detection; PMU samples supply current per pixel as the laser rasters; resistance image computed from constant V. sciencedirect S0026271421000354
  16. iST — Optical Beam Induced Resistance Change (OBIRCH) service overview: temperature gradient → resistance variance; locates metal voids, voids under vias, high-R via bottoms, shorts/leaks. istgroup.com/en/service/obirch