Every ESD kill is either
over-voltage or over-current.
An ESD event dumps a fixed packet of charge into a node. Silicon dies in exactly two ways depending on how that charge is spent: the transient field ruptures a dielectric before current can flow, or the transient current heats a junction or conductor until it melts. Fast events favor the first channel, slow/high-energy events the second. Everything below is organized around that split.
Contents
The two root causes
Strip the acronyms away and there are only two physical destruction channels. They differ in what is exceeded (a critical field vs. a melting temperature) and in which timescale favors them. A well-designed protection network has to win on both: clamp the voltage fast enough and conduct the current with enough robustness.
OVER-VOLTAGE
The transient voltage across a thin dielectric or a reverse junction exceeds its breakdown field before meaningful current flows. The dielectric ruptures; a conductive filament forms.
E = V / d > E_crit (≈ 6–10 MV/cm for SiO₂)- Wins on fast edges — CDM, IEC first peak — where the clamp cannot turn on in time and voltage overshoots.
- Damage is local to the thinnest oxide / sharpest junction nearest the pad.
- Signature: gate leakage, low-ohm gate-to-drain/source short.
OVER-CURRENT
Current is conducted, but I²R heating in a junction, contact, via, or resistor drives local temperature past the melt point. Resistance collapses and a runaway filament shorts the structure.
P = I²R → T > T_melt (Si 1414 °C, Al 660 °C)- Wins on high-energy / longer events — HBM, IEC second peak, MM.
- Quantified per device by the TLP second-breakdown current It2.
- Signature: junction leakage, fused metal/contact, shifted resistor value.
Stress models & delivered current
Each qualification model is just a defined RC source delivering a known charge packet. The headline number is peak current, which sets how hard the over-current channel is pushed, and the rise time, which sets whether the over-voltage channel even gets a chance (a clamp that is fast for HBM can be too slow for CDM/IEC).
| Model | Source network | Std level | Rise time | Peak current | Channel |
|---|
Levels differ between models, so this compares relative severity at the level each part is actually qualified to — which is the real design message: a part that survives 2 kV HBM can still die at 2 kV IEC, because IEC delivers several times the current with a sub-nanosecond edge. MM (200 pF, near-zero series R) is largely deprecated by JEDEC but still appears in legacy specs.
Over-voltage mechanisms V
All four below are the field winning the race against the clamp. Mitigation is about turn-on speed and clamp voltage margin, not about how much current you can sink.
| Mechanism | Physical cause | Where | Onset | Electrical signature | Worst model |
|---|---|---|---|---|---|
| Gate-oxide rupture | Field across thin gate oxide exceeds ~6–10 MV/cm; bonds break, charge traps, a conductive percolation path forms (hard breakdown). | Thinnest oxide nearest the pad — pad-connected I/O FET, receiver input. | ≈ t_ox × 10 MV/cm (thinner oxide → less margin) |
Gate leakage step; low-ohm gate-to-drain/source short. | CDM |
| Junction reverse breakdown | Reverse-biased junction driven past BV; avalanche multiplication localizes — then usually hands off to the thermal channel. | Drain/well junctions, ESD diode reverse leg. | V_rev > BV_junction | Elevated reverse leakage; soft then hard. | CDM/HBM |
| Inter-metal / ILD breakdown | High potential between adjacent metals or across a cap dielectric punctures the inter-layer dielectric. | Tight metal spacing, MIM/MOS caps, crossing buses. | E_ILD > E_crit | Metal-to-metal short; cap leakage. | CDM |
| Clamp overshoot / late trigger | Protection device's trigger voltage (Vt1) or turn-on delay is too high for the edge; core sees the overshoot. A design failure, not a device weakness. | Anywhere downstream of a slow/distant clamp. | Vt1 + L·di/dt > V_core_fail | Core damage with the clamp itself intact. | CDM/IEC |
Over-current mechanisms I
Here the current is being conducted — the question is whether the path can survive the heat. Mitigation is about It2, ballasting, conductor cross-section, and a low-impedance discharge route.
| Mechanism | Physical cause | Where | Governing relation | Electrical signature | Worst model |
|---|---|---|---|---|---|
| 2nd breakdown / filamentation | I²R heat melts silicon; molten Si resistance drops ~30×, current crowds into the hot spot → thermal runaway filament drain-to-source. | Drain junction near surface, gate-drain overlap of the I/O / clamp FET. | I > It2 (TLP) | Low-ohm S-D short; junction leakage. | HBM |
| Metal / contact / via fuse | Surge through an undersized conductor or via array fuses it open; Al can spike into Si at contacts. | Narrow ESD bus, single-via necks, pad routing. | P_fail ∝ t−1/2 (Wunsch–Bell) | Open circuit, or intermittent high-R. | HBM/MM |
| Resistor burnout / shift | Ballast, sense, or series resistor overheats — opens or permanently shifts value. | Poly/diffusion resistors in series with pads (sense, ballast). | ∫I²R dt → T_melt | Parametric shift, open, or drift. | HBM |
| Salicide / current-crowding melt | Without silicide-block + ballast, current crowds at the silicided drain edge and melts before the device width is used. | Silicided drains of I/O / clamp FETs. | non-uniform J → local T_melt | Edge filament; low It2. | HBM |
Which model drives which damage
Susceptibility of each damage mechanism to each stress model. Read it to pick the test that will reproduce a given failure signature.
| Mechanism | Channel | HBM | MM | CDM | IEC 61000-4-2 |
|---|---|---|---|---|---|
| Gate-oxide rupture | V | Lo | Med | Hi | Hi |
| Junction reverse breakdown | V→I | Med | Med | Hi | Med |
| Inter-metal / ILD breakdown | V | Lo | Lo | Hi | Med |
| Clamp overshoot / late trigger | V | Lo | Med | Hi | Hi |
| 2nd breakdown / filamentation | I | Hi | Hi | Med | Hi |
| Metal / contact / via fuse | I | Hi | Hi | Lo | Hi |
| Resistor burnout / shift | I | Hi | Med | Lo | Hi |
| Salicide / crowding melt | I | Hi | Hi | Med | Hi |
Pattern: the field channel tracks edge speed (CDM, IEC), the thermal channel tracks delivered charge / duration (HBM, MM, IEC 2nd peak). CDM is the odd one for metal-fuse — too short to fuse a bus, but lethal to oxide.
Signature → root cause → next test
Start from what the curve tracer / leakage data shows on the failed unit, then converge.
| Observed signature | Likely mechanism | Channel | Confirm with |
|---|---|---|---|
| Gate leakage, low-ohm G–D/G–S short, no S–D damage | Gate-oxide rupture | V | vf-TLP / CDM; EMMI at gate; check clamp turn-on delay. |
| Low-ohm drain-to-source short, junction leakage | 2nd breakdown / filamentation | I | TLP It2 vs. spec; EMMI/OBIRCH at drain edge. |
| Open or intermittent high-R on a supply/IO trace | Metal / contact / via fuse | I | X-ray / FIB the bus; extract route R, count vias. |
| Parametric drift in a sense/ballast resistor | Resistor burnout / shift | I | TLP the pin; inspect poly/diff resistor. |
| Core damaged but clamp device intact | Clamp overshoot / late trigger / broken discharge path | V | Diff vs. a known-good pin on same clamp; extract series R/L to clamp. |
| Fails only multi-strike (survives 1st zap) | Latent damage accumulating (IEC ≥10 strikes) | V/I | Repeat-strike TLP; leakage trend per pulse. |
Mapping to the SV* pins
From the pin/ESD diagram, the SVID signals sit in two domains, and the high-voltage outputs SVDH / SVTOH are exposed to both damage channels. That is why a single test rarely tells the whole story here.
Over-voltage risk
On a fast edge (CDM, IEC first peak) the main prgVddioCDG clamp is far across the VDDIO net and may turn on too late. The HDrive PMOS gate/oxide nearest the pad sees the overshoot → oxide rupture. Signature would be gate leakage / low-ohm gate short with the clamp intact.
Confirm: vf-TLP / CDM; EMMI at the HDrive gate; measure L·di/dt + R from pad to clamp.
Over-current risk
On HBM, current must reach prgVddioCDG. If a prgVddioSwitch 1 kΩ leg or the prgGpioR floating-well switch sits in series, the path is strangled and current crowds into the HDrive drain junction → 2nd breakdown. Signature: low-ohm drain short, low It2.
Confirm: TLP It2 on SVDH→PGND / →VDDIO both polarities; diff vs. a clean VDDIO pin; OBIRCH the filament.
Diagrams & references
Authoritative, shareable sources for the mechanism figures and waveform diagrams referenced above. Linked rather than copied to respect the publishers' rights — open these for the canonical illustrations.
- MechanismsIdentifying EOS and ESD Failures in Semiconductor Devices — oxide rupture & filament figures (Electronic Design)electronicdesign.com/power-management/article/21799782
- MechanismsESD protection design for I/O libraries in advanced CMOS — three fundamental damage mechanisms, 6–10 MV/cm oxide field, 30× Si melt resistance drop (ScienceDirect)sciencedirect.com/science/article/abs/pii/S0038110108001664
- WaveformsHBM vs. IEC 61000-4-2 — side-by-side current waveform comparison (TI app note SLYT492)ti.com/lit/an/slyt492/slyt492.pdf
- WaveformsIs ±2 kV HBM enough? — HBM/IEC source networks & peak-current table (Macnica / Semtech)macnica.co.jp/en/business/semiconductor/articles/semtech/149173
- WaveformsHBM vs. IEC 61000-4-2 rise-time & clamp turn-on discussion (TI E2E)e2e.ti.com → interface forum 359524
- System ESDApplying system-level IEC 61000-4-2 stress on ICs — clamp scaling, VF-TLP (~200 ps) (Monthly Pulse / Sofics)monthly-pulse.com/2021/06/22/applying-system-level-esd-iec-61000-4-2-stress-on-ics
- StandardsESD Association — component standards: ANSI/ESDA/JEDEC JS-001 (HBM), JS-002 (CDM)esda.org · jedec.org
- OverviewElectrostatic discharge — general models & protection overview (Wikipedia)en.wikipedia.org/wiki/Electrostatic_discharge
Numbers in the model table are nominal per the source networks (HBM 100 pF/1.5 kΩ; IEC 150 pF/330 Ω; CDM self-charged, package/size dependent; MM 200 pF/≈0 Ω). Treat CDM peak current as order-of-magnitude — it scales strongly with package and field-plate area.