ESD Debug Guide: telling current damage from voltage damage

Why CDM-vs-HBM is really a pulse-width question, and how the RC-triggered clamp's two mechanisms map onto the two failure channels.

Scope: SV* / VDDIO domain on the attached pin map · Clamp type in diagram: RC-triggered active MOSFET rail clamp · Channels throughout: V = over-voltage / field I = over-current / thermal

1. Guide — is CDM vs HBM a current/voltage test, or a duration trade-off?

Short version: it's a useful first guess, but the clean variable is duration, not the model name. The model names just sit at opposite ends of the pulse-width axis, and pulse width is what decides whether heat or field reaches its limit first.

1.1 The heuristic, and why it's only a heuristic

The common shorthand — HBM = current damage, CDM = voltage damage — holds often enough to be useful: HBM failures are usually thermal (second breakdown, metal/contact fusing), and CDM failures are usually dielectric (gate-oxide rupture)^[6]. But it is a correlation, not a definition, and it breaks in two ways:

A CDM strike can still cause thermal damage, and an HBM strike can rupture an oxide — the model only shifts the probability of each channel.
Pass/fail on CDM vs HBM also confounds polarity, the discharge path, and which internal node sees the stress. It tells you a pin failed, not which physical limit it hit.

Cleaner experimentTo actually separate current from voltage, sweep pulse width directly: TLP (≈100 ns) gives you the thermal second-breakdown current It2; vf-TLP (≈1–5 ns) exposes transient turn-on and overshoot. The pulse-width sweep is the discriminator; CDM and HBM are just two points on it^[3].

1.2 The real axis: pulse width (Wunsch–Bell)

Thermal failure is governed by how much power a structure can absorb before a junction or conductor reaches its melt point, and that limit is a strong function of pulse width. The Wunsch–Bell relation^[1] gives three regimes of power-to-failure P_f versus pulse width τ:

Adiabatic (very short): P_f ∝ 1/τ — no time for heat to spread, so it takes enormous power to fail thermally.
Thermal-diffusion (mid): P_f ∝ 1/√τ — the classic Wunsch–Bell slope.
Steady-state (long / EOS): P_f ≈ const.

The consequence is the key to your question: as pulses get shorter, the thermal limit climbs steeply, but the dielectric (field) limit barely moves with time — an oxide ruptures at roughly its critical field whether the pulse is 1 ns or 100 ns^[2]. The device fails at whichever limit is lower. So there is a crossover: long pulses fail thermally (current), short pulses fail dielectrically (voltage).

Figure 1. The device fails at the lower of the two limits. Where the steep thermal curve sits above the flat oxide limit (short pulses → CDM region) the part dies by over-voltage; where the thermal curve drops below it (long pulses → HBM/EOS) it dies by over-current. Schematic, after Wunsch–Bell / Dwyer^[1].

1.3 So what does "sustained longer" damage?

Longer events deliver more ∫ I²R dt into the same structure, so the answer is unambiguous: longer duration favors the thermal / over-current channel.

Damage that a longer-duration event preferentially causes
Mechanism	Why duration matters	Channel
Junction 2nd breakdown / filamentation	Heat must accumulate until Si melts and resistance collapses (~30×) into a runaway filament; needs time at current.	I
Metal / contact / via fusing	Wunsch–Bell `t^−1/2` regime — the longer the pulse, the lower the current that fuses the conductor.	I
Ballast / sense resistor burnout	Integrated power raises the resistor past its melt/shift point.	I
EOS (ms+)	Steady-state thermal regime — pure heat; not ESD anymore but the same channel taken to its limit.	I

The flip side: the shortest events (CDM, IEC first peak) don't have time to deposit that heat, so they fail things by field instead — oxide rupture, junction overshoot — which is exactly why the HBM↔TLP thermal correlation breaks down once a non-thermal oxide mechanism enters^[3].

1.4 With a voltage clamp present: CDM AC-couples past it

This is the part your note got right. A clamp limits the pad voltage, but it does so with finite turn-on delay and finite impedance, and CDM's sub-nanosecond edge has frequency content up into the GHz. Three things let CDM bite even behind a working clamp:

Turn-on delay. An RC-triggered clamp that turns on in a few ns is fast for HBM but can lag a <0.4 ns CDM edge — the node overshoots before the big FET conducts^[9].
L·di/dt overshoot. Even while conducting, the residual voltage is V_hold + I·R_on + L·di/dt. CDM's huge di/dt across bond/bus inductance can push this above the gate-oxide breakdown voltage — a documented CDM failure mode^[4].
Capacitive (AC) coupling. i = C·dV/dt: a fast edge drives displacement current through C_gd / Miller / well caps straight into internal gates. The clamp pins the DC level on the rail; the high-frequency transient still arrives at the oxide the clamp never sees.

✦

Net answer to 1.1Yes — once a clamp is in the loop, CDM is even more a voltage/field problem than a current problem. The clamp absorbs the bulk charge (the current channel), so what's left to do damage is the fast residual that couples and overshoots into oxide — field channel. HBM, by contrast, parks the clamp in steady conduction, so its risk is the current the clamp and bus must survive.

1.5 Quick stress contrast

Peak current share

Edge speed, duration and delivered current at each model's qualification level
Model	Rise time	Duration	Peak current	Tends to fail

Note: rise/duration bars are normalized per column; CDM peak current is order-of-magnitude (package/size dependent). The orthogonality is the point — CDM = fast & brief (field), HBM = slow & long (thermal), IEC = fast edge and long tail, so it threatens both^[7]^[8].

2. Root cause with the attached clamp — AC trigger + snapback

The clamp cells repeated across your pin map (IS_AVNWELL, Pvdd2AnaVddio, PVDD2POC, prgVddioCDG) are all the same structure. Reading it correctly is what lets you assign a failure to the current or the voltage channel.

2.1 What the clamp in the diagram actually is

The resistor + capacitor, inverter, and large output FET with a parallel diode is a textbook RC-triggered active MOSFET rail clamp^[5], usually paired with pad steering diodes (one up to the rail, one up from ground)^[4]. It is a transient-triggered clamp: it responds to the rising edge of an ESD event, not to a fixed voltage.

Figure 2. The clamp's three behaviors. A the intended fast path: the RC node follows the edge and the inverter drives the big FET hard on within nanoseconds^[5]. B the backstop: if the edge outruns the trigger, MBIG's parasitic NPN snaps back (current/avalanche-triggered). C the leak the clamp can't stop: fast dV/dt couples through C_gd onto an internal gate.

2.2 Two mechanisms: AC trigger and snapback backstop

Your read — "combo of AC + snapback" — is exactly the operating principle. They are two different ways the same cell can turn on:

The clamp's two turn-on mechanisms
Mechanism	Trigger	Speed / behavior	Risk
AC trigger primary	Displacement current in the RC network (responds to `dV/dt`) — not to a fixed voltage.	Turns MBIG on in a few ns; stays on for the RC time-out (hundreds of ns), clamping the rail in triode at low voltage^[10].	If the RC/gate drive is slower than the edge (CDM), it lags → overshoot before conduction.
Snapback backstop	Avalanche at the drain junction fires the parasitic lateral NPN (current-triggered).	Higher trigger `Vt1`, then a low holding voltage; carries large current once on.	Non-uniform conduction → filamentation if un-ballasted; `Vt1` can exceed oxide BV in advanced nodes^[2].

2.3 Two phases = two damage channels

The single most useful way to assign root cause: a clamp event has a turn-on/overshoot phase and a conduction phase, and each phase owns one damage channel.

Figure 3. Same clamp, two stresses. The fast CDM edge overshoots the oxide limit during the turn-on delay — a voltage kill in the first nanosecond. The slow HBM event is clamped low but parks the cell in conduction for ~150 ns, where the surviving question is current vs. It2 — an over-current kill.

Phase → channel → where the damage lands
Phase	What's happening	Channel & failure	Driven by
Turn-on / overshoot	Before MBIG (or snapback) fully conducts, the node rises to `Vt1 + L·di/dt`; fast edge AC-couples to internal gates.	Over-voltage — oxide rupture, junction overshoot.	CDM, IEC first peak (fast edges).
Conduction	MBIG/snapback ON, sinking the discharge; residual `V = Vhold + I·Ron + L·di/dt`.	Over-current — 2nd breakdown, metal/contact fuse.	HBM, MM, IEC second peak (long tails).

2.4 Diagnosis & fixes by phase

If it fails fast (CDM / vf-TLP) but survives HBMYou're in the turn-on/overshoot phase → voltage channel. Look at trigger speed and overshoot: shrink the effective RC for the edge or use a capacitance multiplier / drain-gate coupling to speed turn-on^[9], lower Vt1, add a local secondary clamp at the receiver, a small series gate resistor, and dual CDM diodes placed right at the pad.

If it fails long (HBM / 100 ns TLP)You're in the conduction phase → current channel. Look at It2 and the discharge path: enlarge MBIG, add ballasting/silicide-block, widen the bus and via arrays, and — critically for your SV* case — get the series 1 kΩ (prgVddioSwitch) and the floatwell switch out of the ESD path so current actually reaches prgVddioCDG.

✓

SV* takeawayBecause SVDH / SVTOH sit behind a far clamp and programmable isolation, they're exposed in both phases. Qualify on vf-TLP/CDM (overshoot) and TLP/HBM (It2), and a pad-local dual-diode + secondary clamp that bypasses the 1 kΩ/floatwell defeats both phases at once.

3. References

D. C. Wunsch & R. R. Bell, "Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors Due to Pulse Voltages," IEEE Trans. Nucl. Sci. NS-15, 1968 — power-to-failure vs. pulse width (adiabatic / √τ / steady-state regimes), with V. M. Dwyer.
researchgate.net — Wunsch–Bell curve figure
"ESD protection design for I/O libraries in advanced CMOS technologies," Solid-State Electronics — three fundamental damage mechanisms; oxide field 6–10 MV/cm; molten-Si resistance drop ~30×; dielectric BD before snapback in scaled nodes.
sciencedirect.com/science/article/abs/pii/S0038110108001664
"HMM–TLP correlation for system-efficient ESD design," Microelectronics Reliability — 100 ns TLP ↔ 2nd HMM peak (thermal); correlation breaks when a non-thermal gate-oxide (over-voltage) mechanism enters.
sciencedirect.com/science/article/abs/pii/S0026271411005117
US Patent 10,937,782 — CDM robustness limited by L·dI/dt overshoot during discharge exceeding the gate-oxide breakdown voltage.
patents.google.com/patent/US10937782B2
"A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS," Microelectronics Reliability — RC-triggered rail-clamp operation (RC node → inverter → big FET), drain-gate coupling, TLP sizing.
sciencedirect.com/science/article/abs/pii/S0026271404001520
"Identifying EOS and ESD Failures in Semiconductor Devices," Electronic Design — oxide rupture as the main CDM breakdown mechanism; filament/short imagery.
electronicdesign.com — article 21799782
"Protecting your IC from system-level ESD," TI Analog Applications Journal (SLYT492) — HBM vs. CDM vs. IEC 61000-4-2 waveform & peak-current comparison.
ti.com/lit/an/slyt492/slyt492.pdf
"Is ±2 kV HBM sufficient?" Macnica / Semtech — HBM (100 pF/1.5 kΩ) and IEC 61000-4-2 (150 pF/330 Ω) source networks, rise times and peak-current ratios.
macnica.co.jp — semtech/149173
"CDM protection design for CMOS applications using RC-triggered rail clamps," EOS/ESD Symposium — multi-RC fast trigger; DTSCR overshoot ~1.5 V at 7 A; secondary clamps for CDM.
researchgate.net — publication 224084076
US Patent 10,594,135 — RC-triggered ESD clamp: stays ON for the whole HBM event clamping below ~4 V, no false trigger on fast supply ramp, self-shutdown ~450 ns.
patents.google.com/patent/US10594135B2

Figures 1–3 are original schematics drawn for this note; underlying physics and parameters are sourced from the references above. Numbers are nominal — confirm clamp Vt1, RC time constant and bus L/R against the actual cell and layout before acting.