74xx Logic Kit Reference22 parts · 25 pages · Letter portrait
74HCxx / 74LSxx IC Kit
All 22 device types in the kit, drawn as the logic they contain. The bold
number on each card is the page — printed in the corner of that page — carrying its
full pinout, internal diagram and truth table.
74LS · Schottky TTL74HC · CMOS
74HCxx / 74LSxx IC Kit — pinout & function referenceSymbol index1 / 25
74HCxx / 74LSxx IC Kit
Pinout and internal function diagram for all 22 device types in the
Minidodoca 22-value / 44-piece kit — 2 pieces of each part, plus DIP-14, DIP-16 and DIP-20 sockets.
One page per part: the package pinout, the logic that is actually inside the die, and the truth table.
The two families in this kit
74LS — low-power Schottky TTL
VCC 4.75 – 5.25 V only (5 V, ±5 %).
Input LOW ≤ 0.8 V, input HIGH ≥ 2.0 V.
A floating input reads as HIGH and picks up noise — tie unused inputs to VCC through 1 kΩ, or to GND.
Output sinks ~8 mA but sources only ~0.4 mA — wire LEDs from VCC into the pin, not from the pin to ground.
Draws several mA even when nothing is switching.
74HC — high-speed CMOS
VCC 2 – 6 V. Runs at 3.3 V or 5 V.
Switching threshold sits near VCC/2; inputs draw essentially no current.
Inputs must still never be left open — an open CMOS input oscillates and heats the chip.
Outputs source and sink ±4 mA (±6 mA on the '245 and '595), swinging rail to rail.
Near-zero idle current, but a 74HC input is not guaranteed to see a 74LS HIGH of 2.4 V —
use a 74HCT part when an LS output has to drive a CMOS input.
How to read these pages
Pinout drawings
Drawn top view: notch up, pin 1 at the top left, numbering counter-clockwise.
That is exactly how the part looks sitting in a breadboard.
Power pins are not always the corners — the 74LS90 puts VCC on pin 5 and GND on pin 10.
NC means no connection: leave it open, do not use it as a tie point.
Function diagrams
Numbers in circles are package pin numbers.
A bubble on a gate input or output, or a bar over a name
(CLR), means that signal is active LOW.
A small triangle at a flip-flop input marks the clock; C1 / 1D is the standard
IEC notation for "this D input is controlled by clock 1".
Before you power anything up: put a 0.1 µF ceramic capacitor between VCC and GND
right at each chip, check the notch orientation, and never let two outputs drive the same node.
Series-resistor every LED (220 – 470 Ω at 5 V).
74HCxx / 74LSxx IC Kit — pinout & function referenceOverview2 / 25
74LS00
Quad 2-input NAND gate
74LS · low-power Schottky TTL
Pinout — DIP-14
At a glance
Function
Y = A · B
Gates per package
4 independent 2-input gates
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the four gates)
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
74HCxx / 74LSxx IC Kit — pinout & function reference74LS003 / 25
74HC00
Quad 2-input NAND gate
74HC · high-speed CMOS
Pinout — DIP-14
At a glance
Function
Y = A · B
Gates per package
4 independent 2-input gates
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the four gates)
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
74HCxx / 74LSxx IC Kit — pinout & function reference74HC004 / 25
74LS02
Quad 2-input NOR gate
74LS · low-power Schottky TTL
Pinout — DIP-14
At a glance
Function
Y = A + B
Gates per package
4 independent 2-input gates
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the four gates)
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
74HCxx / 74LSxx IC Kit — pinout & function reference74LS025 / 25
74HC02
Quad 2-input NOR gate
74HC · high-speed CMOS
Pinout — DIP-14
At a glance
Function
Y = A + B
Gates per package
4 independent 2-input gates
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the four gates)
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
74HCxx / 74LSxx IC Kit — pinout & function reference74HC026 / 25
74LS04
Hex inverter
74LS · low-power Schottky TTL
Pinout — DIP-14
At a glance
Function
Y = A
Inverters per package
6
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the six inverters)
A
Y
0
1
1
0
74HCxx / 74LSxx IC Kit — pinout & function reference74LS047 / 25
74HC04
Hex inverter
74HC · high-speed CMOS
Pinout — DIP-14
At a glance
Function
Y = A
Inverters per package
6
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the six inverters)
A
Y
0
1
1
0
74HCxx / 74LSxx IC Kit — pinout & function reference74HC048 / 25
74HC14
Hex Schmitt-trigger inverter
74HC · high-speed CMOS
Pinout — DIP-14
At a glance
Function
Y = A
Inverters per package
6
Power
VCC = pin 14, GND = pin 7
Why Schmitt
Cleans up slow, noisy or bouncing edges — the input must cross a different threshold going up than coming down.
Function diagram — what is inside
Logic tables
Truth table (each of the six inverters)
A
Y
0
1
1
0
Schmitt-trigger thresholds (VCC = 4.5 V, 25 °C)
Parameter
Typ
VT+ (rising)
2.7 V
VT− (falling)
1.6 V
Hysteresis
1.1 V
74HCxx / 74LSxx IC Kit — pinout & function reference74HC149 / 25
74LS08
Quad 2-input AND gate
74LS · low-power Schottky TTL
Pinout — DIP-14
At a glance
Function
Y = A · B
Gates per package
4 independent 2-input gates
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the four gates)
A
B
Y
0
0
0
0
1
0
1
0
0
1
1
1
74HCxx / 74LSxx IC Kit — pinout & function reference74LS0810 / 25
74HC08
Quad 2-input AND gate
74HC · high-speed CMOS
Pinout — DIP-14
At a glance
Function
Y = A · B
Gates per package
4 independent 2-input gates
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the four gates)
A
B
Y
0
0
0
0
1
0
1
0
0
1
1
1
74HCxx / 74LSxx IC Kit — pinout & function reference74HC0811 / 25
74LS32
Quad 2-input OR gate
74LS · low-power Schottky TTL
Pinout — DIP-14
At a glance
Function
Y = A + B
Gates per package
4 independent 2-input gates
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the four gates)
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1
74HCxx / 74LSxx IC Kit — pinout & function reference74LS3212 / 25
74HC32
Quad 2-input OR gate
74HC · high-speed CMOS
Pinout — DIP-14
At a glance
Function
Y = A + B
Gates per package
4 independent 2-input gates
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the four gates)
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1
74HCxx / 74LSxx IC Kit — pinout & function reference74HC3213 / 25
74LS86
Quad 2-input exclusive-OR gate
74LS · low-power Schottky TTL
Pinout — DIP-14
At a glance
Function
Y = A ⊕ B
Gates per package
4 independent 2-input gates
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Truth table (each of the four gates)
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
0
74HCxx / 74LSxx IC Kit — pinout & function reference74LS8614 / 25
74LS74
Dual D-type flip-flop with preset and clear
74LS · low-power Schottky TTL
Pinout — DIP-14
At a glance
Trigger
Positive edge (LOW → HIGH) on CLK
PRE / CLR
Asynchronous, active LOW, override the clock
Typical use
Divide-by-2, edge synchroniser, 1-bit register
Power
VCC = pin 14, GND = pin 7
Logic tables
Function table
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*
H*
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
hold
hold
* Both LOW is a forbidden state — the outputs are not complementary.
Function diagram — what is inside
74HCxx / 74LSxx IC Kit — pinout & function reference74LS7415 / 25
74LS90
Decade counter (÷2 and ÷5 sections)
74LS · low-power Schottky TTL
Pinout — DIP-14
At a glance
Trigger
Negative edge (HIGH → LOW) on CKA / CKB
BCD decade
Clock into CKA (14), tie QA (12) → CKB (1). Outputs QD QC QB QA.
Bi-quinary ÷10
Clock into CKB (1), tie QD (11) → CKA (14). Gives a 50 % duty output on QA.
Power
VCC = pin 5, GND = pin 10 — not the usual corners!
Logic tables
BCD count sequence (CKA in, QA→CKB)
0
1
2
3
4
5
6
7
8
9
QD
0
0
0
0
0
0
0
0
1
1
QC
0
0
0
0
1
1
1
1
0
0
QB
0
0
1
1
0
0
1
1
0
0
QA
0
1
0
1
0
1
0
1
0
1
Reset / set inputs
R0(1)
R0(2)
R9(1)
R9(2)
Result
H
H
L
X
Reset to 0000
H
H
X
L
Reset to 0000
X
X
H
H
Set to 1001 (9)
L
X
L
X
Counts
X
L
X
L
Counts
Function diagram — what is inside
74HCxx / 74LSxx IC Kit — pinout & function reference74LS9016 / 25
74LS47
BCD to 7-segment decoder / driver (open collector)
74LS · low-power Schottky TTL
Pinout — DIP-16
At a glance
Display type
COMMON ANODE only — outputs sink current, they do not source it
Series resistors
Required on every segment (220–470 Ω at 5 V)
LT (pin 3)
Lamp test: LOW turns every segment on
RBI (pin 5)
Ripple-blank in: blanks a leading zero
BI/RBO (pin 4)
Dual purpose: drive LOW to blank the digit, or read it as ripple-blank out
Power
VCC = pin 16, GND = pin 8
Logic tables
Decoded segments (0 = segment ON / output LOW)
Dec
D
C
B
A
a
b
c
d
e
f
g
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
1
2
0
0
1
0
0
0
1
0
0
1
0
3
0
0
1
1
0
0
0
0
1
1
0
4
0
1
0
0
1
0
0
1
1
0
0
5
0
1
0
1
0
1
0
0
1
0
0
6
0
1
1
0
1
1
0
0
0
0
0
7
0
1
1
1
0
0
0
1
1
1
1
8
1
0
0
0
0
0
0
0
0
0
0
9
1
0
0
1
0
0
0
1
1
0
0
Inputs 10–15 produce unique but non-numeric patterns.
Function diagram — what is inside
74HCxx / 74LSxx IC Kit — pinout & function reference74LS4717 / 25
74LS138
3-to-8 line decoder / demultiplexer
74LS · low-power Schottky TTL
Pinout — DIP-16
At a glance
Outputs
Active LOW — the selected line goes LOW, the other seven stay HIGH
Address weight
A = LSB (pin 1), C = MSB (pin 3)
Enables
G1 must be HIGH and both G2 inputs LOW
Cascading
The three enables let you build a 1-of-24 or 1-of-32 decoder with no extra glue
Power
VCC = pin 16, GND = pin 8
Logic tables
Function table (H = HIGH, L = LOW, X = don't care)
G1
G2A
G2B
C
B
A
Output LOW
L
X
X
X
X
X
none — all HIGH
X
H
X
X
X
X
none — all HIGH
X
X
H
X
X
X
none — all HIGH
H
L
L
0
0
0
Y0
H
L
L
0
0
1
Y1
H
L
L
0
1
0
Y2
H
L
L
0
1
1
Y3
H
L
L
1
0
0
Y4
H
L
L
1
0
1
Y5
H
L
L
1
1
0
Y6
H
L
L
1
1
1
Y7
Function diagram — what is inside
74HCxx / 74LSxx IC Kit — pinout & function reference74LS13818 / 25
74HC138
3-to-8 line decoder / demultiplexer
74HC · high-speed CMOS
Pinout — DIP-16
At a glance
Outputs
Active LOW — the selected line goes LOW, the other seven stay HIGH
Address weight
A = LSB (pin 1), C = MSB (pin 3)
Enables
G1 must be HIGH and both G2 inputs LOW
Cascading
The three enables let you build a 1-of-24 or 1-of-32 decoder with no extra glue
Power
VCC = pin 16, GND = pin 8
Logic tables
Function table (H = HIGH, L = LOW, X = don't care)
G1
G2A
G2B
C
B
A
Output LOW
L
X
X
X
X
X
none — all HIGH
X
H
X
X
X
X
none — all HIGH
X
X
H
X
X
X
none — all HIGH
H
L
L
0
0
0
Y0
H
L
L
0
0
1
Y1
H
L
L
0
1
0
Y2
H
L
L
0
1
1
Y3
H
L
L
1
0
0
Y4
H
L
L
1
0
1
Y5
H
L
L
1
1
0
Y6
H
L
L
1
1
1
Y7
Function diagram — what is inside
74HCxx / 74LSxx IC Kit — pinout & function reference74HC13819 / 25
74LS164
8-bit serial-in, parallel-out shift register
74LS · low-power Schottky TTL
Pinout — DIP-14
At a glance
Serial input
A AND B — tie one HIGH and drive the other, or use B as a gate
Trigger
Positive edge on CLK (pin 8)
Clear
CLR (pin 9) LOW zeroes all eight stages, independent of the clock
Outputs change while shifting — use a '595 instead if you need glitch-free outputs
Power
VCC = pin 14, GND = pin 7
Function diagram — what is inside
Logic tables
Function table
CLR
CLK
A
B
QA
QB … QH
L
X
X
X
L
all L
H
L
X
X
hold
hold
H
↑
H
H
H
shifted right
H
↑
L
X
L
shifted right
H
↑
X
L
L
shifted right
74HCxx / 74LSxx IC Kit — pinout & function reference74HC16421 / 25
74HC165
8-bit parallel-in, serial-out shift register
74HC · high-speed CMOS
Pinout — DIP-16
At a glance
Direction
A is loaded into the first stage, H into the last; H appears at QH first
Serial input
SER (pin 10) — feed the previous chip's QH here to cascade
Outputs
QH (pin 9) and its complement QH (pin 7)
Typical use
Read 8 buttons/switches with 3 microcontroller pins
Reading order
Pulse SH/LD LOW then HIGH to snapshot the inputs, then clock 8 times
Power
VCC = pin 16, GND = pin 8
Logic tables
Function table
SH/LD
CLK INH
CLK
Action
L
X
X
Parallel load A–H (asynchronous)
H
L
↑
Shift one place toward QH
H
L
L
Hold
H
H
X
Hold — clock inhibited
Function diagram — what is inside
74HCxx / 74LSxx IC Kit — pinout & function reference74HC16522 / 25
74HC595
8-bit shift register with output latch and 3-state outputs
74HC · high-speed CMOS
Pinout — DIP-16
At a glance
Why two clocks
SRCLK shifts, RCLK publishes — outputs stay stable while data is shifting in
Cascading
QH' (pin 9) is the overflow bit; chain it to the next chip's SER
Drive
±6 mA per output — fine for an LED with a series resistor
Power
VCC = pin 16, GND = pin 8
Logic tables
Function table
SRCLR
SRCLK
RCLK
OE
Action
L
X
X
X
Clear the shift register
H
↑
L
L
Shift SER in one place
H
L
↑
L
Copy shift register → output latch
H
X
X
H
QA–QH go high-impedance (latch keeps its data)
Typical wiring to a microcontroller
Pin
Name
Connect to
14
SER
Data out
11
SRCLK
Clock
12
RCLK
Latch / strobe
10
SRCLR
VCC (tie HIGH if unused)
13
OE
GND (tie LOW if unused)
9
QH'
SER of the next '595
Function diagram — what is inside
74HCxx / 74LSxx IC Kit — pinout & function reference74HC59523 / 25
74LS245
Octal bus transceiver with 3-state outputs
74LS · low-power Schottky TTL
Pinout — DIP-20
At a glance
Channels
8 bidirectional, non-inverting
Drive
Up to 24 mA sink — designed to drive a loaded backplane
Careful
Never enable two drivers onto the same bus at once — bus contention
Typical use
Level buffering / direction switching between a CPU and a peripheral bus
Power
VCC = pin 20, GND = pin 10
Logic tables
Function table
OE
DIR
Operation
L
H
A data → B bus
L
L
B data → A bus
H
X
Both buses isolated (high-Z)
Function diagram — what is inside
74HCxx / 74LSxx IC Kit — pinout & function reference74LS24524 / 25
74HC164
App note — wired as a single D flip-flop (D, CLK, Q)
74HC · high-speed CMOS
This kit has no 74HC74, so the only dedicated D flip-flop is the bipolar
74LS74 on page 15. When you want a CMOS flip-flop — and want to keep the
'74's preset and clear free for set/reset work later — take the first stage of a 74HC164.
Each of its eight stages already is a positive-edge D flip-flop; you simply use stage A
and ignore the rest — its full internal view is on page 21.
Wiring — DIP-14, top view
Connections
Pin
Name
Wire it to
1
A
D input
2
B
VCC — makes D = A
3
QA
Q output
8
CLK
Clock, rising edge
9
CLR
VCC — LOW clears Q
14
VCC
+5 V (2 – 6 V)
7
GND
0 V
4-6, 10-13
QB…QH
Leave open
What you are left with
Numbers in circles are 74HC164 package pins.
Resulting flip-flop
CLR
CLK
D
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
hold
Positive-edge triggered, exactly like a '74 — but with no /Q output.
Worth knowing
No /Q
The '164 brings out only true outputs. If you need the complement,
invert QA through a spare gate on the 74HC04 or 74HC00.
Free async reset
/CLR on pin 9 is already an active-LOW asynchronous clear.
Tie it HIGH to ignore it, or drive it and you have D, CLK, Q and reset.
Free delay taps
QB…QH are the same data 2…8 clocks later — useful as an
edge synchroniser or a shift-register debounce without adding a part.
Why not the others
The 74HC595's first stage is not brought out — its
serial output is 8 clocks late — and the 74HC165 loads the wrong direction.
74HCxx / 74LSxx IC Kit — pinout & function referenceApp note25 / 25